`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:20:39 09/15/2011 
// Design Name: 
// Module Name:    Bus 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Bus(Read_Data_1, Read_Data_2 ,A_Enable, B_Enable, Result_Enable, reg1_Enable, reg2_Enable, regWrite_Enable);

wire bus, ALU_A_Bus, ALU_B_Bus [15:0];
input Read_Data_1, Read_Data_2, A_Enable, B_Enable, Result_Enable, reg1_Enable, reg2_Enable, regWrite_Enable;

TristateBuffer(Read_Data_1, ALU_A_Bus, A_Enable);
TristateBuffer(Read_Data_2, ALU_B_Bus, B_Enable);


endmodule
